A problem can exist in a zero-power device, such as an SRAM (static random access memory) that operates from a power supply, which regularly supplies power to the device, and then is required to operate from a battery when a power supply failure is detected. The problem is often isolated to the power supply detection circuit which upon detecting the power supply failure, can cause multiple switchovers between the power supply output and the battery output as the power supply output voltage decays.
An example of such a power supply voltage detection circuit is shown in FIG. 1, which shows an electrical diagram of a comparator 100 that compares the power supply output voltage, Vcc, to the battery voltage, Vbat. For purposes of the description to follow below, the nominal power supply voltage is 5 volts and the nominal battery voltage is 3 volts. When the comparator 100 detects that Vbat>Vcc, the comparator 100 provides a signal to the battery switching logic described below to switch the source of power from the power supply to the battery. Since there are many other comparator configurations that can be utilized as a power supply detection circuit other than that shown in FIG. 1, a complete description of the operation of the comparator 100 of FIG. 1 is not being provided herein.
FIG. 2 is an electrical diagram of the battery switching logic 200 used to switch power to the SRAM from the power supply to the battery. The battery switching logic 200 of FIG. 2 utilizes large geometry p-channel switches identified as M1 and M2. M1 and M2 are used to switch power to an SRAM connected to output Vout, shown in the block diagram 300 of FIG. 3, from an internal power source Vcc, and an external power source Vbat. M1 is used to switch the external power source Vbat to Vout, and M2 is used to switch the internal power source Vcc to Vout. When M1 and M2 switch, i.e. one turns on while the other turns off, oscillation between selecting the internal power source Vcc and the external power source Vbat can occur. The problem is due to the capacitance of the large geometry p-channel switches that can combined be about 30 to 40 pF (pico-farads) as will be described below. Since there are many other battery switching logic configurations that can be utilized a more comprehensive description of the operation of the battery switching logic 200 is not being provided herein.
FIG. 4 is an electrical diagram showing an input ESD (electrostatic discharge) circuit 400 utilized on integrated circuits having inputs and/or outputs that are sensitive to electrostatic discharge damage. A bonding pad 402 is connected to the cathode terminal of a substrate diode 404, to the anode terminal (drain terminal) of an n-channel diode-connected MOS transistor 406, and to one terminal of an ESD resistor 408. The anode terminal of substrate diode 404 and the cathode terminal (gate and source terminals) of n-channel diode-connected MOS transistor 406 are connected to Vss (ground). The second terminal of the ESD resistor 408 is connected to the cathode terminal of a substrate diode 410, to the anode terminal (drain terminal) of an n-channel diode-connected MOS transistor 412, and to the comparator 100 input and switching circuit 200 input being supplied the battery voltage through bonding pad 402. The anode terminal of substrate diode 410 and the cathode terminal (gate and source terminals) of n-channel diode-connected MOS transistor 412 are connected to Vss (ground). The ESD resistor 408 has a typical resistance of from 100 to 300 Ω (ohms). Positive going and negative going voltage spikes created by static electricity are effectively suppressed by the typical input ESD circuit 400 in a manner well known in the art.
The battery voltage Vbat is supplied to both the comparator 100 and the switching logic 200 through the bonding pad 402 and the input ESD circuit 400. The process of charging, as an example M2 high, resulted in a significant voltage drop across the ESD resistor 408. The resultant voltage drop at the input of the comparator 100 reduced the detected Vbat voltage below the current Vcc voltage, causing the switching logic 200 to switch back to the internal power supply.
The effect of this switching back and forth is shown in FIG. 5 which is a graph 500 depicting the operation of the comparator 100 and switching logic 200. The vertical axis represents voltage and the horizontal axis represents time. Waveform 502 depicts the power supply voltage Vcc decaying because of a power supply failure and approaching the battery voltage Vbat. Waveform 504 depicts the resultant voltage drop at the output of the input ESD circuit 400, corresponding to the input to comparator 100, when Vbat=Vcc and the comparator 100 triggers the battery switching circuit 200, and thereafter when Vbat>Vcc and the battery switching circuit 200 is retriggered. Waveform 506 depicts the output of the switching circuit Vout. After having switched back to the internal power supply, the power supply output voltage continues to slump, the comparator 100 again detects Vbat>Vcc, and the switching logic 200 switches to the external battery. The oscillation continues for several hundred micro-seconds until the detected value of Vbat at the output of the input ESD circuit 400 no longer falls below the detected value of Vcc.
The problem described above is generated because the output Vout provides approximately 100 mA (milli-amperes) of current to the SRAM, the internal power required to power the comparator 100 and the battery switching circuit 200 is between 1 and 5 mA while switching, and settles to less than 100 nA (nano-amperes) after switching, as compared to the current required to the input of the comparator, which is less than 1 nA. Prior art methods of overcoming the problems noted above often included separating the detection circuit from other circuits, so as to provide multiple bonding pads and a separate input ESD circuits for any voltage sensitive circuit function. Because most integrated circuit layouts are constrained by size and the number of bonding pads that can be provided, this solution is not always cost effective.
What is therefore needed is a means for supplying more than one circuit having voltage sensitive and non-voltage sensitive functions and sharing a common input using a single bonding pad. What is also needed is a space efficient method of providing multiple input ESD circuits for the circuits connected to the common bonding pad.